Positioning control system for a machine that performs work on a moving part

ABSTRACT

A programmable and manually operable control system for controlling the position of a machine relative to a workpiece so the machine may perform work at various locations on the workpiece while the workpiece is moved by the conveyor. The system includes a pair of synchro resolvers which provide output signals indicative of the position of the machine relative to a datum position and a pair of synchro resolvers which provide output signals indicative of the position of the conveyor relative to the datum position. The outputs of the machine indicating resolvers provide the inputs to the conveyor indicating resolvers and the outputs of the conveyor indicating resolvers are compared with command signals that are generated by a continuously recycling counter which has been preset by signals from a memory so the displacement between selected locations on the workpiece and the machine is electrically measured without using differential mechanical gearing. The control system is arranged so the machine will move synchronously with the workpiece, independently of the workpiece, and synchronously with the workpiece while the machine is moving from one preprogrammed location to a new preprogrammed location on the workpiece.

United States Patent [19] Anger et al.

in], 3,775,654 NOV. 27, 1973 [541 POSITIONING CONTROL SYSTEM FOR A MACHINE THAT PERFORMS WORK ON A MOVING PART [75 lnventors z ErnestG. Anger, Yaurvatosat; Giles J. Richards, Menomonee Falls; John F. Bloodgood, Fond Du Lac; Roy J. Geiger, Cedarburg, all of Wis.

[73] Assignee: Square D Company, Park Ridge,

Ill.

[22] Filed: Nov. 29, 1972 21 Appl. No.: 310,;99

[62] Division of Ser. No. 248,944, May 1, 1972, which is a division of Ser. No. 146,110, May 24, I971, Pat.

Williamson 318/599 X Primary Examiner-B. Dobeck Attorney -Harold J. Rathbun et al.

[57] ABSTRACT A programmable and manually operable control systern for controlling the position of a machine relative to a workpiece so the machine may perform work at various locations On the workpiece while the workpiece is moved by theconveyor. The system includes a pair of synchro resolvers which provide output signals indicative of the position of the machine relative to a datum position and a pair of synchro resolvers which provide output signals indicative of the position of the conveyor relative to the datum position. The outputs of the machine indicating resolvers provide the inputs to the conveyor indicating resolvers and the outputs of the conveyor indicating resolvers are compared with command s ignalsthatare generated by a continuously recycling counter which has been preset by signals from a memory so the displacement between selected locations on the workpiece and the machine is electrically measured without using differential mechanical gearing. The control system is arranged so the machine will move synchronously with the workpiece, independently of the workpiece, and synchronously with the workpiece while the machine is moving from one preprogrammed location to a new preprogrammed location on the workpiece.

3 Claims, 10 Drawing Figures COM PATENTEDNuvmmrs 3,775,654

SHEET 2 0F 6 500 KHZ REF PATENTEUNUVZ? ms mwm sum 5 or g 1"46,l l0, filed May24, 1971 now Pat. No: 686,556.

The present invention relates topositioning control, and more particularly to a control system for positioning a machine at desired positionsalong a workpiece I while the workpiece is moving along apredetermined path relative to a datum position.--

In the field-of positioning control, various systems have been proposedfor moving acontrolled tmember in accordance with instructions stored'within amemory so that work may be automatically performed-upon a workpiece. In these prior systems, .the maximum range of movement of the controlledmember is usually limited to a few feetand generally the workpieceis maintained stationary whileworkis-performed by thec'ontrolled member. Thus the systems as heretofore known:

are not particularly suited to control the'positioning of a machine which performs work at variouspositions along the entire length of the body of'anautomotive vehicle while the body is transported? bya moving con-' veyorthrough a work station.

A technique commonly practiced in factories whichmanufacture or assemble mass-produced automotive vehicles requires that the components of the subassembliesfor a complete vehicle be assembled to each other while the components arecarried by a suitable support that is moved by a conveyor past the various work stations where parts are secured to each other to complete the subassembly. For example, the fabrication of asubassembly, called the body of the vehicle, is normally accomplished by accurately positioning the components on a fixture, called a body truck, and moving'the body truck past work stations where the parts of the body are welded together Theweldingof the parts is accomplished by welding guns which are manually mo'ved'to the desired positions alongthebody partsto securethe parts together by a series of spot welds which are sequentially formed as the gun is positioned "at spaced locations along the body parts. While the manual formation of spot welds has proven'satisfactory, it is objectionable in that it notonly depends uponthe'skill ofthe gun operator to accurately locate the welds and teassure that the proper number of welds are made between the parts, but it also occasionally requires the operator to assume physically uncomfortable and ex hausting positions to make the welds.

while it is apparent that the machine as controlledby the control system as will be hereinafter describedmay be readily modified to perform-a variety of operations upon workpieces while the workpieces are moving" along a predetermined path,-the control system is described as controlling the positioning of'a resistance move continuously. Thismeans that any malfunction of a machine which would require the conveyor to be stopped would be highly objectionable. One type of failure or malfunction which may occur in a-resistance spot welding. apparatus is the weld electrodes may be stuck to the parts which are being welded together. When thistype offailure occurs and the apparatus is being manually operated, minimal difficulties result as the human operator merely moves along the line until the welding electrodesare freedfrom" the body part. However, when'thistype offailure occurs ina machine controlled-welding apparatus, more disasterous consequences may occurbecauseofthe capability of'the machine to pullthe partssfrom their'position on the body truck or to mutilate'theaparts beyond use.

' Tosuccessfully perform work upon aworkpiece-car ried' bya'conveyor, a=rnachine which'performsthe work must be capable ofoperatingfinseveral modes. lnone 'mode of operationrthemachine must be capable of 20 to apart'that is carriedby a moving'conveyor, a multiple axis control of the machine,- i.'e., six axis control, may I be readily obtained by duplicating? the necessary components of the control 'forthe-longitudinal axis with theexceptionthatithesynchro resolvers,which are used to synchronize the movement ofthe-machin'e'with the movement -of"the-'conveyor, are eliminated.

It is an object of the present invention to provide a control'system-for a machinewhich will automatically perform'work'on workpieces that are carried on a moving "conveyor.

Another object is to provide a control system'for a machine whichwillcontrol the position of the machine relative'to preselected-positions on a part so the ma-- chine may perform work on the part while the part is movedby the conveyor.

A further object is to'provide a control system for'positioning 'a machine *at*desired positions along 'a'workpiece while the workpiece is moving along a predeterwelding gun to form spot welds between parts of'an au-.

tomotive vehicle body as the body parts are transported by a moving body truck along a conveyorline. One of the problemspresented in synchronizinglhe operationof a machine with the position of parts carried on aform work on body parts which are carried on a moving conveyor in an automotive vehicle factory is that to maximize production, it is imperative that the conveyor workpiece while the workpiece is"moving'along=a predetermined pathrelative to'a datum-position witha means'forelectrically synchronizing-the movement of the machine with respect to the workpiece, with said synchronizing means including a fi'rstpair of synchro resolvers'which provide'an output indicative of thepo sition of the machine relative to the datum position, a, second pair of synchro resolvers which providean out put indicative of theposition' of the workpiece relative 'to the datum position, a means which is arranged to be energized by the output of the first pair of resolvers and provide an input to the second pair of resolvers and a means which is arranged to compare the outputs of the second resolvers with recycling command position signals and cause the command signals to correspond with the outputs of the second pair of resolvers when the machine is required to move synchronously with the workpiece along the path of movement of the workpiece.

A still further object is to provide a control system for positioning a machine at desired positions along a synchro resolvers'each of which provides an output signal indicative of the position'of the workpiece relative to the datum position, a means for causing the inputs of the second pair of'resolvers to be energized by the outputs of the first pair of resolvers and a means which compares both the order of occurrence and the interval between the occurrence of the output signals of the second pair of resolvers and a command signal and provides an error signal which has a magnitude dependent upon the interval between the signals and a direction indication controlled by the order of occurrence of the signals.

v A still further object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece. is moving along a pre- 7 determined path relative to a datum position with a means for electrically synchronizing the movement of the. machine with respect to the workpiece that includes a pair of synchro resolvers each of which provides an output indicative of the position of the machine relative to the datum position, a second pair of synchro resolvers eachvof whichprovides an output signal indicative of the position of the .work piece relative to'the datum position, a means for causing'the inputs of the secondpair of resolvers to be energized by the outputs of the first pair of resolvers and a means which compares both the order of occurrence and the interval between the occurrence of the output signals of the second pair of resolvers and a command signal and provides an error signal which has a magnitude dependent upon the interval between the signals and a direction indication controlled by the order of occurrence of thesignals and to provide the control with a means which is manually operable to cause the machine to move independently of the signals. I

Another object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position witha means which provides a feedback signal that is indicative of the relative positions of the workpiece and the machine relative to the datum position, a means including'a recycling counter which provides a command signal phase that is preset to be indicative of a preselected position on the workpiece at which the machine is to be positioned while the workpiece .is moving'relative to the datum position and a hold means responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the hold means is activated. 1

An additional object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions of the workpiece-and the machine relative to the datum position, a means including a counter which provides a command signal that is indicative of a preselected position on the workpiece at which the machine is to be positioned while the workpiece is moving relative tothe datum position, a jog means for causing the machine to move at either of two selected speeds independently of the workpieces when the jog means is activated, said jog means including circuitry that is responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the jog means is activatedand means which will cause the movement of the machine to increase at a preselected rate when the jog means is actuated and to abruptly decrease when the jog means is deactivated.

A further object is to provide'a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions of the workpiece and the machine relative to the datum "position, a means including a counter which provides a command signal that is indicative of a preselected position ,on the workpiece at which the machine is to be positioned while the-work-' piece is moving relative to the datum position and a jog means for causing the machine to move independently of the workpieces when the jog means is activated, said jog means including circuitry that is responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the jog means is activated.

Another object is to provide a control system forvcontrolling the energization of an electric motor which drives a machine to desired positions along'a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions ofthe machine and workpiece relative to the datum position, a means which provides a command signal that is indicative of a preselected commanded position on the workpiece at whichthe ma chine is to be positioned, said feedback and command signals consisting of a predetermined voltage change which occurs at predetermined instants during each cycle of a reference wave and respectively varying in time during each cycle depending upon the relative positions of the machine and workpiece from the datum position and the location of the desired position relative to the datum position, means for comparing both the order of occurrence and the interval between the occurrence of the voltage changes of the feedback and the command signal and providing an output signal pulse during each half cycle which has a width dependent upon the interval between said pulses and a polarity indicative of the order of occurrence of the pulses, and a deceleration means for controlling the direction of rotation and the speed of rotation of the motor in response to the polarity andwidth of the pulses, said decrease the ratio between the width of the pulses and the energizationof the motor as the width of the pulses decreases during periods when the machine is slowing down as the machine is approaching the commanded position. a f

Further objects and features of the invention will be readily apparent to those skilled in the art from the following specification and from the appended drawings illustrating certain preferred embodiments in which:

FIG. 1 shows in block diagram form a controlsystem embodying the features of the present invention.

FIG.'2 is a schematic and block diagram of the circuitryused to compare the outputs of the position detecting resolvers and'the'command positionsignal provided bythe components in FIG, 1.

FIG-.3 is-a graphical'representationshowing'the time relationships of signalsin the-circuit shown in FIG 2. FIG; 4 is aschematic and block' diagramof the circuitry used tocause the machine in FIG. 1* to operate .in a hold position and/ora jogging-mode of'operation.

FIG. 5 is a schematic diagram of the circuitry used to control the energization and de-energization of a drive motor for the machine in FIG.- 1 when the jogging mode of operation is initiated and terminated.

FIG. 6 is a schematic diagram of a circuit which controls the energization of the drive motors for the machine in response to the output signal from the comparator circuit in FIG. 1. I

FIGS. 6A and 6B are graphs illustrating the change in the energization of the drive motor for a machine in FIG. 1 as the machinemoves toward a commanded position.

FIGS. 6C and 6D are graphs with time as a reference, illustrating the manner in which a capacitor in FIG. 6 is charged in response to error pulses.

7 Referring now to the drawings, and more particularly to FIG. 1 thereof, the control system of the present invention is therein illustrated as controlling the position of a machinelO relative to the position of a pair of workpieces 11 and 12, which represent parts of an automotive vehiclebody, that are carried on a longitudinally movable fixture known in automotive'assembly' plants as a body truck 13. In conventional practices, as followed in automotive assembly plants, a succession of spaced trucks 13 are continuously moved along-a path dictated by a pair of spaced rails 14 past work stations where work is performed on the parts carried by the trucks. Each of the trucks 13, as used with the present system, has a block 15 secured at one of its longitudinal sides with an opening 16 accurately located in the block 15 relative to the workpieces 11 and'12. The opening 16 is located to receive a pin 17 that projects upwardly from a longitudinally movable chain 18 which is moved by the truck 13 horizontally along a path parallel to the rails 14 in the direction indicated by the arrow 19 as the truck'13 moves from an upstream end 20 of the work station, wherein themachine 10 is located, to the downstream end 21 of the work station. The chain 18 isarranged so that as a truck 13 enters the upstream end 20 of the work station, the pin *celeration means being arranged'to exponentially ini the chain 18, including the pin 17 may be moved by a means, not shown, upstream to the upstream end 20 where it will bein a position to engage a block 15' on a subsequent truck 13, as the truck 13* enters the work station. J

The machine 10 includes a base 22 that is movable along the parallel rails 23 along a path-that is parallel and'spacedfrom the path of movement of the truck 13.

The base 22 is moved by a lead screw 24 through a suit"- able travelling nut, not shown,,which is secured to the base 22' and arranged to be driven by the lead screw 24'. The lead screw 24 is rotated through a suitable speed reducing gear box 25 by an electric motor 26; A vertical stanchion27; which is securedon the base 22-, supportsvan arm-28i'The arm'28issupportedby the stanchion 27 so that the arm'28 may move horizontally along a horizontal axis that extends vertically to' the path determinedby the rails 14; and rotate about. its

horizontal axis. Securedon the free end of the arm 28 isapair ofelectrodes, indicated as 29, which are ar- I rangedto engage and spot'weld the workpieces 11 and 12: together. The electrodes 29are movable by a suitable mechanism30=in an arcuate path'along a vertical axis as wellas an arcuate path that extends horizontally. The horizontalarm 28 'is also movable along a vertical-axis onthe stanchion'27. Thus the movement provided by the base 22' along the axis dictated by the rails 23' the vertical, horizontal and rotational movement of the arm 28'about the stanchion 27 and the movement provided'by the mechanism 30 on the end of the arm 28'about the horizontal and vertical axes, will permit electrodes 29 to move along six axes relative to the workpieces 11 and 12.

A system which will'control the horizontal position-- ing of the machine 10 along an axis parallel to the movement of The body truck 13 and the workpieces 1 1 and 12 includes a memory 31 which is preferably of the retentive typeso that information stored'therein will not be lost in the event of a power failure. The memory 31, as used herein, is acommercially available type and includes an array of bistable state magnet cores which are capableof being programmed to'have information stored therein. The information which is stored in; the

cores of the memory 31 includes positional information which will dictate the desired positions of the welding electrodes29relative to the workpieces 11 and 12, functional information which controls the operation of the welding electrodes, information which will control suitable circuitry within an operator control station 17 will be projected upwardly, by a means not shown,

into the opening 16 tocause the chain as-well as the pin 17 to be moved by the truck 13 downstream to the end 21 whereat the pin 17 is retracted from the opening 16 in the block- 15 as the truck 13 carrying'the fabricated workpieces l1 and 12 leaves the work station, so that module 32which suppliesv input signals to a sequence control circuit module 33 and ahold-jog circuit module 34; Whilethe control module '32 may be programmed to cause the control system to'operate the machine 10 in modes other than are hereindescribed; for purposes of understanding of the operation of the circuits which will belater described, the control module 32 is described as providingsuitable output signals which will cause the machine to operate in an automatic mode, an indexing mode, a teach and jogging mode and a mode designated as hold.

The control module 32,- when programmed to cause the machine to operate in the index or automatic mode, will provide signal inputs to the sequence control module 33 which will cause the digital command information stored within a the memory 31 to be read out through gates'35, 36 and 37 andbe respectively supplied as input information to a coarse command counter 38, a fine commandcounter 39, circuits within a function module 40 and circuits within an end of program and miscellaneous function module 41. The counters 38 and 39 are 1000 bit recirculating counters and receive a continuous train of 500 KHZ reference inputpulsesfrom a system timing module 42. When the continuous train of 500 KHZ pulses is fed into the counters 38 and 39 and the counters 38 and 39 are reset bythe reference input pulses and preset by the information from the memory 31, the train of 500 HZ pulses will appear at the output of the most significant bit of the counters 38 and 39 which will have a predetermined phase relationship with respect to a 500 HZ reference input signal'pulses and thereby in effect diof the position of the pin 17 relative to the datum position includes a coarse feedback resolver 46 and a fine feedback resolver 47. Each of the resolvers 44-47 is a synchro type resolver and includes a rotatable shaft, a pair of input windings wound in spaced quadrature and an output winding that provides a cyclic output voltage signal which varies in phase relative to the phase of the voltage across its input windings with the angular position of the shaft when the input windings are respectively energized from an alternating current source by equal magnitude alternating voltages that are in quadrature. 1

- The shaft of the coarse feedback resolver 44 is connected through a gear box 48 to be rotated by the'lead screw 24 one complete revolution when the machine is moved twice the distance between the ends and 21. The shaft of the fine feedback resolver 45 is connected through a gear box 49 to be rotated by the lead screw twenty revolutions for each revolution of the shaft of the coarse resolver 44. The shaft of the coarse feedback resolver '46 is connected through a gear box 50 to be rotated in response to the movement of the chain 18 one complete revolution when the pin 17 is moved twice the distance between the ends 20 and 21. Similarly, the shaft of the fine resolver 47 is connected through a gear box 51 to be rotated in re- Sponse to the movement of the chain twenty revolutions for each revolution of the shaft of the coarse resolver 46. v

A sin/cos generator circuit module 52, which is controlled by the timing module 42, supplies one of the input windings of the resolvers 44 and 45 with. a 500 HZ sine wave input that is in phase with the 500 HZ reference sine wave input to the counters 38 and 39 and the other of the pair of input windings of the resolvers 44 and 45 with a 500 HZ sine wave of equal amplitude,

butlagging the reference sine wave by 90 (cos). With I this excitation, the outputs of the resolvers 44 and 45 will vary in phase relative to the reference sine wave with the position of their respective shafts. The 500 HZ sine wave output of the resolver 44 is-supplied as an input through a lead 53 to one of the windings of the resolver 46 and is integrated by an integrator circuit module 54 and supplied to the other input winding of the resolver 46as a 500 HZ sine wave of equal amplitude, but lagging in phase by 90 (cos) with the excitation voltage supplied by the lead 53. Similarly, the 500 HZ sine wave output of the resolver 45 is supplied as an input through a lead 55 to one of the pair of input windings of the resolver 47 and is integrated by a circuit module 56 and supplied to the other input of the winding of the resolver 47 as a 500 HZ sine wave of equal amplitude but lagging in phase by 90 (cos) with the excitation voltage supplied by the lead 55.

The 500 HZ sine wave outputs from the resolvers 46 and 47 are respectivelyamplified, clamped and rectified by circuits within switch modules 57 and 58 to appear as a pulse train that is similar to the outputs of the coarse command counter 38 and the fine command counter 39. The outputs of the switch modules 57 and 58, which are respectively called a coarse feedback signal CFB and a fine feedback signal FFB, are supplied as inputs to a coarse comparator module 59 and a fine comparator module 60, which also respectively receive inputs from the coarse command counter 38 and the fine command counter 39.

The output of the coarse command counter 38, hereinafter referred to as a coarse command signal CC, is a logic l to 0 transition at the trailing edge of each cycle of the 500 HZ voltage wave. The l to 0 signal change can be made to occur at any one of 1000 different instants during each cycle of the 500 HZ reference voltage wave so that the coarse command counter 38 can be programmed to provide 1000 distinct coarse command signals for each revolution of the coarse resolver 44 or 46. Similarly, the fine command counter 39 can be programmed to provide 1000 distinct command l to 0 logic signals, or fine command signals PC, for every one-twentieth revolution of the coarse resolver 44 or 46. Therefore, if it is assumed that the total distance between the ends 20 and 21 is 200 inches and both the machine 10 and the truck 13 are capable of moving 200 inches, then the relative range of movement between the workpieces 11 and 12 and the electrodes 29 will be 400 inches. Thus as the coarse command counter 38 is capable of providing 1000 distinct coarse command signals over the entire range of movement (1 revolution of the coarse resolvers 44 and 46)which is 400 inches, and the fine command counter 39 is capable of providing 1000 distinct fine command signals over one-twentieth of the total range (20 inches), the linear axis will have a resolution of 0.02 inches and the system has the capability of being programmed to 20,000 distinct command positions within the 400 inch range of relative movement between the machine 10 and the truck 13.

As will be later described, the circuitry within the coarse comparator 59 compares the coarse feedback signal CFB with the coarse command signal CC and provides an output error signal to aswitch module 61 which is dependent upon the order of occurrence and the time interval between the l to 0 change'in the signals from the compared signals which will cause the motor 26 to be energized to rotate either in the forward or reverse directions, depending on the order of occur- 9v rence of the l to signals at a predetermined rate when the time interval between the signals is greater than a preselected interval. Also, the fine comparator 60 compares the fine feedback signal FFB with the fine command signal FC and provides 'an output error signal to the switch module 61 which is dependent on the order of occurrence and the interval between the l to 0 change in the signals which it compares. The output error signal from the fine comparator 60 to the switch module 61 will cause the motor 26 to be energized to rotate in the forward or reverse directions depending upon thev order of occurrence of the 'lto O signal ,changes of the'compared signals at a rate dependent signal from a tachometer 64 that is driven by the motor 26 to limitthe energization of the motor 26. I

The motor 26, when energized, will rotate the lead screw 24 through the gear box 25 to move the electrodes 29 which are supported by the base 22 and rotate the shafts of the resolvers 44 and 45 in a direction which willreduce the error signals as detected by the comparators 59 and 60. When the electrodes 29 are in their commanded position relative to the workpieces 11 and 12, the l to 0 signal changes of the coarse feedback signal CFBand the, coarse command signal .CC will be in phase and the I to 0 signal change of the fine feedback signal FFB will be in phase with the fine command signal PC which will cause the switch module 61 to supply an in position signal to the logic circuitry within an end of motionmodule 65. The module 65 in response to the in position input signal supplies a signal to the function module 40 which will initiate the operation of a weld sequence timer and cause the electrodes 29 to spot weld the workpieces 11 and 12 together. During the weld interval, when the spot weld is being formed, the workpieces 11 and 12 will be moving through the work station and the feedback outputs of the coarse and the fine resolvers 46 and 47 will be continuously changing. The fine comparator 60, in response to the changing fine feedback signal FFB, will provide an output through the circuits in the switch module 61 and the deceleration module 62, which causes the servo-drive amplifier 63 to provide the motor 26 with an energization that is exactly sufficient to move the machine 10 synchronously with the truck v13. The synchronous movement of the machine 10 causes the coarse and fine resolvers 44 and 45 to supply I a changing input to the coarse and fine resolvers 46 and 47 which in turn reduces the changing coarse and fine feedback signal input to the comparators 59 and so system to minimize damages which could occur in that the welding electrodes 29 remain in their programmed position as they are forming a spot weld between the workpieces 11 and 12.

The function module 40, at the end of the weld interval, will supply an input throughthe lead 66 to the sequence control module 33 which causes the sequence control module 33 to sequence the memory 31.and'

open the gates 35-37 to reprogram the coarse and the finev command counters 38 and 39, and-the function module 40, so that the command counters 38 and 39 provideoutput command signals which will require the machine 10 to move to a new preprogrammed position relative to the workpieces 11 and 12. The coarse and fine comparators 59 and 60 in response to the changed coarse and fine command signal will provide an output signal which will cause the motor 26 to be energized to reduce the error signal in a manner previously described as the machine 10 moves to its newly commanded-position relative to the workpieces 11 and 12.

At the end of the program, that is, when all the required spot welds have been made between the parts 11 and 12"at the positions dictated by the information stored within the memory 31, the end of pro'giam module 41 will supply a signal through a leadl67 to the switch modules 57 and 58. Also at the end of the program, the memory 31 will supply suitable inputs through the gates 35 and 36 to the coarse and fine command counters 38 and 39 which will cause the counters to supply coarse and fine command signals which will requirethe machine 10 to move upstream to its start position at the end 20 where it will await the entry of a subsequent truck 13 carrying unassembled work? pieces into the work station. The circuitry within the switch modules 57 and 58 is arranged so that a signal input from the module 41 will cause the switch modules 57 and 58 to respond to the outputs of the resolvers 44 and 45 instead of the outputs from the resolvers 46 and 47 and permit the machine 10 to move independently of the chain 18 upstream to the end 20. During the movement of the machine 10 to the end 20, the truck 13 carrying the assembled workpieces will continue to move toward the end 21. The pin 17 is disengaged from the opening 16 when the truck 13 leaves the work station at the end 21, so that the chain 18 may be moved upstream and position the pin 17 at the end 20 where it will engage the opening 16 in a subsequent truck 13 as the subsequent truck 13 enters the work station.

The foregoing operation constitutes a description of the operation of the control system when the control module 32 is programmed so that the machine 10 will operate in the automaticmode. The indexing mode of operation is provided in the control system to check the information stored within the memory 31 during periods when the conveyor which moves the body truck 13 is stopped.-The program within the memory 31 may be checked by merely pressing a button in the control module 32 which'will cause the machine 10 to move from one preprogrammed position to its next programmed position and maintain its position until the indexing button is again depressed, which will sequence the memory 31 one step and require the machine 10 to move to a new position. Thus the machine10 may be sequenced through its programmed steps to determine if the information within the memory 31 corresponds to a program which will locate the spot welds between the workpieces 11 and 12 at their desired locations.

A hold mode of operation is included in the control event an emergency should occur while the machine 10 is operating in its automatic mode and it becomes necessary to stop the conveyor line which moves the trucks 13; The hold mode of operation may be initiated-at any.

time by activating a suitable hold switch inthe control module 32. If the machine 10 is moving toward a new position on the workpieces l1 and 12, when the hold mode of operation is initiated, the coarse and fine command signals will be reset to correspond to the coarse and fine feedback signals, in a manner to be later describedin detail, and the movement of the machine 10 will be' synchronized with the movement of the conveyoras the conveyor coasts to a stop.

The initiation of the hold switch will cause the holdjog module 34 to supply-a signal for a brief time interval, i.e., 380 milliseconds, to the comparators 59 and 60 which will block the operation of the comparators 59 and 60 and cause the comparators 59 and 60 to supply a zero output error signal which will permit the motor 26 to decelerate. During the 380 millisecond time interval, the Hold-jog module 34, in response to feedback signals from the resolvers 46 and 47, will supply inputsignals to the counters 38 and 39 which will preset the counters 38 and 39 when the coarse and fine feedback signals change from I to so that the coarse and the fine command signals will be in phase with the coarse and the fine feedback signals. The pre-setting of the counters 38 and 39 will occur approximately 190 times during the 380 millisecond interval after which the comparators 59'and 60 will cause the motor to be energized to an extent necessary to cause the machine to move synchronously with the truck 13 as the truck l3 coasts to a stop. 7

The teach mode of operation is included in the control system to permit the machine 10 to be manually controlled in its movementto a variable number of discreet positions relative tofthe workpieces 11 and 12 to which the machine 10 can be later caused to move in automatic play-back mode. The operators control module 32 is provided with a suitable switch which will cause thesystem to operate in the automatic or teach mode and jog switches which, when operated, will energize the motor 26 to jog machine 10 in either a fast or slow jogging speed. The teach mode of operation may be initiated by activating the teach and jog switches in the control module 32. When the teach and jog switches are activated, the machien 10 will move to a desired position on the workpieces 11 and 12 and the jog-hold circuit will operate in a manner which will be later described. During the movement of the machine 10 in the jogging mode, .the coarse and fine command signals will be preset to correspond to the coarse and fine feedback signals. When the machine 10 is in its desired position, and a suitable second switch within the control module 32 is activated, the information which is stored within the coarse and fine counters 38 and 39 will be transferred into one bank of the memory 31. When the machine 10 is again jogged to a new position, the coarse and fine command signals again will be preset to correspond to the coarse and fine feedback signals so that the information which corresponds to the new position may be transferred out of the command counters 38 and 39 into the next sequenced bank of the memory 31. The movement of the machine 10 to any number of desired locations is repeated until the desired number of spot weld locations are recorded in the memory 31.

rotation of the motor 26 progressively increases to the 7 selected jog speed when the jog switch is initially actuated and abruptly reduced when the jog switch is deactivated to aid in the accurate positioning of the electrodes 29 on workpieces 11 and 12.

The circuits as shown in the drawings includes a plurality of solid state logic units designated as NANDS, ANDS, NORS and JK typeflip flops, all of which are well known to those skilled in the art, and provide outputs in response to inputs as follows. A NAND provides a Boolean logicoperation which yields a logic 0 output when all of its logic input signals are logic'l and a logic 1 output when any of its logic input signals are logic 0. An AND provides a Boolean logic operation which yieldsa logic l output when all its logic input signals are logic 1 and a logic 0 output when any of its logic input signals are logic 0.- A NOR provides a Boolean logic operation which yields a logic 1 output when all of its logic input signals are logic 0 and a logic 0 output when any of its logic input signals are logic 1. A flip flop I is a circuit that has two stablestatesand the capability When the jog switches are operated in the control module 32, the jog hold circuit 34 will supply a suitable input to the switch module 61 which will cause the drive motor 26 to rotate in either the forward or re-' verse direction at either a fast or slow speed, depending upon the actuation of the jog switches. The circuitry within the jog-hold module 34 is arranged so that the of changing from one state to another with the application of a control signal and remaining in that state after removal of the signals. A JK flip flop is a flip flop having two inputs designated as J and K and a toggle designated as T which, upon a logic 1 to 0 change at its toggle T with a logic 1 on its .1 input and a logic 0 on the K input, will set the flip flop in the ON state and with a logic 0 on its 1 input and a logic 1 on the K input will set the flip flop in its OFF state. The JK flip flops as used herein also include a set input designated by a letter S which is not controlled by the signals appearing at the toggle T and will switch the flip flop to its On state in response to a logic 0 signal at its set input S. A JK flip flop, when in the ON state, will supply a l at its E output and a O at its E output. When in the OFF state, a JK flip flop will supply a 0 at its E output and a l at its E output.

The coarse comparator circuit, shown in FIG. 2 and designated as 59 in FIG. 1, includes a coarse command flip flop CC, a feedback flip flop FB,,a reset flip flop RS, a flip flop FWD designated as a forward flip-flop, a flip flop REV designated as a reverse flip flop, a flip flop SS dsignated as the single shot flip flop, NANDS Nl-NIO, ANDS Al-A2, and a NOR 01. The coarse comparator circuit receives input signals from the coarse command counter 38, the resolver 46 and the timing module 42, illustrated-in FIG. 1, as are typically illustrated by the curves in FIG. 3. The coarse com-. mand counter provides the coarse command signal CC,

the resolver 46 provides the coarse feedback signal CFB and the timing module 42 provides the signals 500 KHZ, REF and lMl-IZ. The forward FWD and reverse REV flip flops have their outputs E and E connected to supply inputs to ANDS A3-A6 which in turn provide inputs to a pair of NORS 02 and 03.

The fine comparator circuit includes a flip flop F FWD which is designated as the fine forward flip flop, a flip flop F REV which is designated as the fine reverse flop, and NANDS which are designated as N11-N20. The fine comparator circuit receives inputs from the fine command counter 39, the resolver 47 and the timing module 42 shown in FIG. 1. The fine command counter provides the fine command signalFC, the resolver 47 provides the fine feedback signal FFB and'the module 42 provides the signals 500 KHZ and lMI-IZ.

coarse feedback resolver .the error signal.

The signalsFWF and REP are synchronizedwith the.

f ne command signal FC.

COARSE COMPARATOR CIRCUIT The NAND N7 has an input 1 connected to the signal source REF and an input 2 connected to an output E of the flip flop RS. The flip flop R8 is turned ON by a 0. input from the 500 KHZ signal on its input S. In its ON state, the flip flop RS supplies a 1 signal at its output E. The source REF supplies a signal pulse that has I a 500 nanosecond duration at a rate of 500 cycles per second. Thus every 500 cycles the output of the NAND CC has its toggle T connected to receive a coarse cominand input signal CCand is. switched to an OFF state upon a ltd Ochange in they signal CC. Similarly,the flip flop FB has'its' toggle connected to receiv'e the coarse feedback signal CFB and is switched to an OFFstate upon a l to 0 change in the signal CFB. The difference in time of occurrence of a l to 0 signal change of the coarse command signal CC and the coarse feedback signal CFB will provide an error signal which is indicative of both the direction and the distance which the .46 must-be rotated to reduce if the machine 10 is positioned so that the coarse feedback signal CFB-changes from 1 to 0 prior to a l to 0 change in the coarse command signal CC, the control will operate to rotatethe resolver, 46 in a direction to reduce the error signal which, for purposes of description, is designated as a reverse direction REV. Similarly, if the coarse command signal CC changes from 1 to 0 prior to a change of l to O of the coarse feedback signal CFB, the control will operate to reduce the error signal and drive the resolver 46 me. forward direction FWD. In FIG. 3, the curves indicate the signals appearing at the inputs and outputs of the designated solid state components relative to a train of 500 nanosecond 0f pulses on a 500 cycles per second reference wave REF, when the control is programmed so the coarse feedback signal CFB changes from 1 to 0 prior to a change of l to 0 of the coarse command signal CC.

The l to 0 signal change of the coarse feedback signal CFB to the toggle T of the flip flop FB causes the flip flop FB to switch OFF and a 1 signal to appear at its output E and a 0' signal at its output E. The 1 signal at output E of the flip flop F8 is supplied to an input 2 of the NAND N3, an input 1 of the NAND N5 and an input 3 of the AND A2. The 0 signal at output E of the flip flop F8 is supplied to the J input of the flip flop REV, an input 2 of the AND Al, and an input 2 of the NAND N1. The NAND N3 through its input 1 also receives an input of '1 from the output E of the flip flop CC which remains in its ON state because the coarse command signal CC on its toggle T has not changed from 1 to 0. Thus as both inputs 1 and 2 of the NAND N3 are l, the output of the NAND N3 switches to 0. The 0 output of the NAND N3 is inverted by a NAND .N4 and is supplied as a l to the K input of the flip flop toggle T input. The AND A2also receives a 1 signal at its input 2 from the flip flop RS output E and a 1 signal at its input 1 from the-output E-of the flip flop CC. As all of the inputs to the AND A2 are now 1, it switches its output to supply a 1 input to the NOR 01 which switches its output from 1 to 0.

The output of the NOR 01 is supplied as a 1 to 0 input signal change to the toggle T and the K input of the flip flop SS.'The flip flop SS, in'response to the 1 to 0 output signal change of the NOR'Ol, switches to an OFF state so that a Osignal appears at its output E and a 1 signal appears at its output E. The l to 0 signal.

change at the output E of the flip flop SS is inverted by the NAND N9 and supplied as a 0 to 1 signal input change to the toggles T of theflip flops FWD and REV.

During theinterval when the flip flop SS is switched ON and-its output E provides a 0 signal, the NAND -Nl0 supplies a l signaltto the input S of the flip flop SS so that theflip flop'SS is conditioned to switch to an OFFstate upon the receipt of a l to 0 input signal change at its toggle T and its input K. The switching of ,the flip-flop SS to an OFF state causes the signal at its outputE to change from 0 to 1. This 0 to 1 signal change is delayed in its transmission to the input of the- NAND N10 by a capacitor C 1 and a resistor R1 so that the NAND N10 continues to supply a 1 signal to'the input S of the flip flop SS after the flip flop SS has switched to an OFF state. After a fixed time delay, as determined by the RC constants of the resistor R] and the capacitor C1, the charge on the capacitor C1 in creases to a value which causes the NAND Nl0'to switch and supply a 0 input signal to the input S of the 4 flip flop SS. The 0 input signal to the input S of the flip flop SS causes the flip flop SS t0 switchto an ON state and the output of the NAND N9 to switch from 1 to O. The output of the NAND N9 is connected to the toggles T of the flip flops FWD and REV. Thus if the coarse'command signal CC has not changed from 1 to 0 prior to the 1 to 0 signal change from the NAND N9, the flip flop FWD will remain ON and the flip flop REV will switch to an OFF stage because of the 1 input signal at its K input and supply a 1 signal at its output E and a 0 signal atqits output E.

As shown in FIG. 3, subsequent to the switching OFF of the flip flop REV and prior to the receipt of the signal change from the signal source REF, the coarse command signal CC changesfrom l to O. V

The l to 0 change of the coarse command signal CC to the toggle T of the flip flop CC causes the flip flop CC to switchOFF sothat a 1 signal appears at its output E and a 0 signal at its output E.-The 1 signal at the output E of the flip flop CC is supplied to the input 2 of the NAND N5 which also receives a 1 input from the flip flop FB at its input, 1 so that the NAND N5 is conditioned to switch when the 500 KHZ signal at its input 3 switches to 1-. When all of the inputs 1, 2 and 3 of the NANDNS are 1, its output switches to O. The 0 output of the NAND N5 is inverted by the NAND N6 and supplied as a 1 to the K input of the flip flop RS which switches to an OFF state upon the receipt of a subsequent l to 0 signal change to its toggle T in the lMl-lZ signal. The flip flop RS when in an OFF stage switches the flip flops CC and F B to their ON states and supplies a 0 signal to the input 2 of the AND 2 which causes the output of the AND A2 to swtich from 1 to 0. The 0 output of the And A2 causes the output of the NOR 01 and the input to the toggle T of the flip flop SS to change T again switches froml to as previously described.

The'l from the 500 KHZ signal, which caused the NAND N to switch and supply a 0 output signal, is also supplied to the input S of the flip flop RS. Therefore when the 500 KHZ signal switches from 1 to 0 subsequent to the switching of the NAND N5, the flip flop RS will switch to its ON state.

Summarizing the foregoing, the switching of the flip flop F8 in response to the l to 0 change in the coarse I feedbacksignal CFB causes a l to be supplied to the K input of the flip flop REV and a l to 0 signal change to be supplied to the toggle T of the flip flop SS. The flip flop SS, resistor R1, capacitor C1 and the NAND N functionas a single shot circuit and after a fixed time delay provide a l to 0 signal change to the toggles T of v 0 signal change to the toggle'T of the flip flop FWD will not change the ON state of the flip flop FWD because of the continuing O that is supplied by the output E of the flip flop CC to the input K of the flip flop FWD. The l to 0 signal change to the toggle T of the flip flop REV however causes the flip flop REV to switch OFF because of the 1 input to its K input. The flip flop REV when OFF supplies a Oat its output E anda lat its output E and remains OFF as long as the duration of the error signal is greater than the fixed time delay pro- I vided by the single shot circuit.

' The ANDS A3,A6 and the NORS 02 and 03 function asthe switch 61 in FIG. 1 as follows. The outputs E of the respective flip flops FWD and REV are respectively connected to the inputs 1 of ANDS A3 and A5. The

output E of the flip flop FWD is connected to an input 2 of an AND A4 and an input 1 of an AND A6. The output E of the flip flop REV is connected to an input 1 of an AND A4 and an input 2 of an AND A6. The ANDS A3 and A4 have their outputs connected to the inputs 1 and 2 of a NOR 02 which has its output connected through a digital to analog converter in the deceleration module 62 in FIG. 1 to control the energization of a motor 26 in a manner which will drive the position resolvers 44 and 45 in the forward direction. Similarly, the ANDS A5 and A6 have their outputs connected to the inputs 1 and 2 of a NOR 03 which has its output connected through the deceleration module 62 to control the energization of a motor 26 in a manner which will drive the position resolvers 44 and 45 in a reverse direction. When both flip flops FWD and REV are ON, the l signals appearing at their respective outputs E will appear as a 1 signal at the inputs of the respective ANDS A4 and A6 so the ANDS A4 and A6 are respectively controlled by signals appearing at their inputs 3 during fine positioning, as will be later described. Further, when both flip flops FWD and REV are ON, the 0 signals appearing at their respective outputs E will cause the ANDS A3 and AS to have O-outputs which permit the NORS 02 and 03 to be con-, trolled by the. outputs of the ANDS A4 and A6.

The flip flop REV, when in an OFF state, supplies a 0 signal at its output E and a 1 signal at its output E. The 0 signal at the output E thereby blocks the switching of the ANDS A4 and A6 in response to the signals from the fine positioning control, as will be later described. The 1 signal from the output E of the flip flop REV is supplied to an input 1 of the AND AS which also receives a signal at its input 2 from the signal source REP. The source REP supplies a signal that is 1 during 20 percent of each cycle of the 500 cycle/sec reference wave and 0 during the remainder of each cycle. Thus the NOR 03 will have a 0 output for 20 percent of the time and energize the motor 26 to drive the motor 26 in the reverse direction to reduce the time duration of the error signal.

FINE COMPARATOR CIRCUIT The solid state logic units in the fine comparator circuit 60 will exist in the following states when the fine comparator circuit 60 is reset. The flip flop FFWD, the flip-flop FREV and the flip flop FRS will be" ON and provide a logic 1 at their respective E terminals and a logic 0 at their E tenninals. The fine command signal FC and the fine feedback signal F FB will each provide a logic l signal to the fine comparator circuit 60. The 1 signal from the fine command signal PC is supplied to the toggle T of the flip flop FFWD and causes the NAND N15 to have a 0 output which is inverted by the NAND N16 and supplied as a l to the K input of the flip flop FREV. The logic l from the fine feedback signal FFB, which is supplied to the toggle T of the flip flop FREV, causes the NAND N19 to have a 0 output which is inverted by the NAND N20 and supplied as a .l to the K input of the flip flop FFWD. The 0 output at the E output of the flip flop F FWD is spplied to the input 2 of the NAND N11 and to the 1 input of the NAND N17 so that the NANDS N11 and N17 will have a continuing 1 output. The 0 output at the E output of the flip flop FREV is supplied to an input 3 of the NAND N17 and an input 2 of the NAND N13 so that the NANDS N13 and N17 provide a continuing I output. The continuing l outputs fromthe NANDS N11 and N13 are inverted by the NANDS N12 and N14 respectively and supplied to the inputs 3 of the ANDS A4 and A6 respectively, so that the NORS 02 and 03 have a continuing 1 output. The output E of the flip flop F R8 is supplied as a l to the inputs S of the flip flop FFWD and the flip flop FREV. During the operation of the fine comparator circuit 60, the ANDS A3 and A5 supply a continuous 1 to the inputs 1.of the NORS 02 and of description, is designated as the reverse direction. Similarly, if the signal from the fine command signal FC changes from 1 to 0 prior to a change of l to 0 in the fine feedback signal F F B, the control will operate to reduce the error signal and drive the fine feedback resolver in a forward direction. In FIG. 3 the curves indicate the signals appearing at the inputs and outputs from the sources indicated and the designated solid components when the machine 10 is positioned so that the fine feedback signal FFB changes from 1 to 0 prior to a change of l to 0 of the fine command signal FC. The continuing l fine command signal through the NANDS N15 and N16 causes a 1 signal input to be present at the K input of the .flip flop FREV so that the change of l to 0 in the fine feedback signal FFB, at the a l toan input 1 of the NAND N20. However, the

NAND N20 continues to supply a l to the K input of the flip flop FFWD as the NAND N20 now receives a at its input 2 from the E output of the flip flop FREV.

The l at the output E of the flip flop FREV is suppliedv .to an input 3 of the NAND N17 and an input 2 of the NAND N13. The output of the NAND N17 does not switch in response to the lat its input 3 because it c ontinues to receive a 0 at its input 1 from the output E of the flip flop FFWD so that the flip flop FRS remains in.

its ON state. The .1 to the input of the NAND N13 permits the state of the NAND N13 to be controlled by the signals from the source REP, which, as shown in FIG. 3, switches from a 0 to 1 72 prior to the switching-of the signal from the fine command signal FC from, 1 to 0 so that thevsignal from the source REP is l during20 percent of each cycle of the fine command signal FC. Thus 72 prior to the signal change in the fine com- .mand signal FC, the NAND N13 has a l on both of its inputs 1 and 2 and thereby supplies a0 input to the NAND N14 which in response thereto supplies a l to the input 3 of the AND A6..As previously described,

' the AND A6 also receives a l at it inputs 1 and 2 from the E outputs of the-flip flops FWD and REV. Thus the output of the AND A6 switches to a l which causes the NOR 03 to supply a 0 signal to the deceleration module 62 which will control the energization of a motor 26 in a manner which will drive the position resolvers'44 and 45 in a reverse direction to reduce the error signal. As shown in FIG. 3, subsequent to the change of the signal from 0 to l of the source REP, the fine command signal FC switches from 1 to 0 The l to 0 change of the fine command signal PC, which is supplied to the toggle T of the flip flop FFWD, causes the flip flop FFWD to switch so that a 1 signal appears at its output E and a 0 signal at its output E.

'The l to 0 change in the fine command signal FC also causes theNAND N15 to supply a l to the input 1 of the NAND N16. However, the NAND N16 continues to supply a l to the K input of the flip flop FREV as the NAND N16 now receives a O at its input 2 from the E output of the flip flop FFWD. The l at the output E of the flip flop FFWD is supplied to an input 1 of the NAND N17 and an input 2 of theNAND N11 so that the NAND N17 now receives a l at each of its inputs 1 and 3 and is conditioned to be switched by the 500 KHZ signals. The 500. KHZ signal is supplied to both the input 2 of the NAND N17 and the input S of the flip flop F RS. Thus during the half cycle when the 500 KHZ signal is l, the input S of the flip flop FR S will be 1 and the output of'the NAND N17 will be 0. The NAND N18 inverts the 0 output of the NAND N17 and supplies a l to the K input of the flip flop FRS which switches to an OFF state when the signal at itstoggle T from the lMHZ signal switches from 1 to 0. The switching to the ON state of the flip flop F RS causes the signal at its E output to change from 1 to 0 and is sup-- plied to the input S of both the flip flops FFWD and F REV. The flip flops FFWD and FREV in response to the 0 sig'nalsat their inputs 5 switch to an ON state and" 18 supply a 0 to the K inputs of the flip flops FFWD and FREV. The flip flops FFWD and FREV when in the ON state also supplya O to the inputs 1 and 3 of the NAND N17 which in response thereto through NAND N18 supplies a 0 to the input K of the flip flopfFRS which causes the flip flop FRS to remain in its ONstate after it is turned ON by a 0 pulse at itsinput S FROM THE 500 KHZ signal on the subsequent change of the lMHZ signal at its toggle T. Thus the flip flops FFWD, FRS, and FREV are all in the ON state so that a subsequent change in the fine feedback signal FFB and the fine command signals from 0 to 1 will cause the NANDS N20 and N16 to respectively supply a l to the inputs K of the flip flops FF WD and FREV and restore the circuit to'its reset state as previously described.

.In view of the foregoing, it is obvious that if the machine 10 is positioned so that the coarse command signal CC changes from .lto 0 prior to a 1 to 0 change in the coarse feedback signal CFB, the control will operate to rotate the resolvers 44 and 45 in a direction to reduce the error signal which, for purposes of description, is designated as the forward direction FWD, in a manner which may be summarized as follows. The flip flop CC will switch OFF in response to the l to 0 change in the coarse command signal CC and cause a Mo be supplied to the K input of the flip flop FWD and a-1 to 0 signal change to be applied to the toggle of the flip flop SS. The flip flop SS,,resistor R1, capacitor C1 and the NAND N10 function as a single shot circuit and after a fixed time delay provide a l to 0 signal change to the'toggles T of the flip flops FWD and REV. If the time delay provided by the single shot circuit is less tha the time delay interval of the error signal, e.g., the interval between 1 to 0 change of the coarse command signal and the l to 0 change in the coarse feed back signal CFB, the l to 0 change to the toggle of the flip flop REV will not change the ON state of the flip flop REV because of the continuing 0 that is applied by the output E of the flip flop F B to the input K of the flip flop REV. The 1 to 0 signal change to the toggle of the flip flop FWD however causes the flip flop FWD to switch OFF because of the 1 input to its K input. The flip flop FWDwhen OFF supplies'a O at its output E and a l at its output E and remains OFF as long as the duration of the error signal is greater than the fixed time delay provided by the single shot circuit.

The flip flop FWD when in the OFF state, supplies a 0 signal at its output E and a 1 signal at its output E. The 0 signal at the output thereby blocks the switching of the ANDS A4 and A6 in response to the signals from the fine positioning control. The 1 signal at the output E of the flip flop FWD is supplied to the 1 input of the AND A3 which also receives a signal at its input 2 from the signal source FWP. The source FWP supplies a signal that is 1 during 20 percent of each cycle of the 500 cycle reference wave after the coarse command signal CC changes from 1 to O, and 0 during the remainder of the cycle. Thus the NOR 02 will have a 0 output for 20 percent of the time and energize the motor 26 to drive the motor-26 at a constant speed in the forward direction to reduce the time duration of the error signal.

If the control is programmed so that the signal from v The l to change of the signal from the fine command signal FC also causes the NAND N15 to supply a lto an input 1 of .the NAND N16. However, the NAND N16 continues to supply a 1 to the K input of the flip flop FREVas the NAND N16 now receives a tinues to receive a 0 atvit s input 3 from the output E of the flip flop FREV so thatthe flip flops FRS remains in its ON state. The l to the input of the NAND Nll permits the state of the NAND N1 1 to be controlled by the signals from the source F WP which existsas a 1 for 72 after the fine command signal FC switches from 1 to 0 so that the signal from the source FWP is 1 during 20 percent of each cycle. Thus during an interval of 72 after the fine command signal has changed to 0, the NAND N11,has a l on all of its inputs and thereby supplies a to the input 3 of the AND A4. As previously described, the AND A4 also receives a 'l at its inputs 1 and 2 from the E outputs of the flip flops FWD and REV. Thus the output-of the AND A4 switches to a l which causes the NOR 02 to supply a 0 signal to the deceleration circuit 62 which will control the energization of a motor 26 in a manner which will drive the position resolver 45 ina forward direction to reduce the error signal. As shown in FIG. 3, subsequent to the change of thesignal from 1 to 0 of the source FWP, the fine feedback signal FFB switches from l to 0. The l to 0 change of the fine feedback signal FFB, which is supplied to the toggle T of the flip flop FREV, causes the flip flop FREV to switch so that a 1 signal appears at its output E and a 0 signal at its output E.

The l to 0 change in the fine feedback signal FFB also causes the NAND N19 to supply a l to the input 1 of the NAND N20. However, the NAND N20 continues to supply a l to the K input of the flip flop FFWD as the NAND N20 now receives a 0 at its input 2 from the E output of the flipflop FREV. The l at the output E of the flip flop FREV is supplied to an input 3 of the NAND N17 and an input 2 of the NAND N13 so that the NAND N17 now receives a l at each of its inputs 1 and 3 and is conditioned to be switched by the 500 KHZ signals. The 500 KHZ signal is supplied to both the input 2 of the NAND N17 and the input S of the flip flop F RS. Thus during the half cycle when the 500 KHZ signal is l, the input S of the flip flop FRS will be 1 and the output of the NAND N17 will be 0. The NAND N18 inverts the 0 output of the NAND N17 and supplies a l to the Kinput of the flip flop FRS which switches to an OFF state when the signal at its toggle T from the IMHZ signal switches from 1 to 0. The switching to the OFF state of the flip flop FRScauses the signal -at its E output to change from 1 toO and is supplied to the input S of both the flip flops FFWD and FREV. The flip flops FFWD and FREV in response to the O signals at their inputs S switch to an ON state and respectively supply a l to theinputs 2 of the NANDS N16 and N20 so that the NANDS N16 and N20 now supply a 0 to the K inputs of the flip flops F FWD and FREV. The flip flops FFWD and FREV when in the ON state also'supply a 0 to the inputs 1 and'3 of the NAND N17 which in response thereto through NAND N18 supplies a 0 to the input K of the flip flop FRS which causes the flip flop F RS to remain in its ON state -0 atits input 2 from the 'E output of the flip flop FFWD.

after it is turned ON by a 0 pulse at its input S from the 500 KHZ signal on the subsequent change of the l to 0 of the l MHZ signal at'its toggle T. Thus the flip flops F FWD, FRS, and FREV are all in the reset state. Subsequent to the resetting of the flip flops FFWD, FRS and FREV, the fine command signal FC and the fine feedback signalFFB will change from O to l and cause the NANDS N20 and N16 to respectively supply a l to the inputs K of the flip flops FFWD and FREV so as to restore the circuit to its reset state, as previously described.

Thus when the interval between the occurrence of the coarse command and feedback signals is greater than the time interval as dictated by the single shot circuit that includes the flip flop SS, the motor 26 will be energized with constant current to operate either in the forward or the reverse directions because of the 20 percent ON time signal pulses provided by the sources FWP and REP. The cross-over at which the control of the energization of the motor 26 is transferred from a control by the coarse feedback signal to the fine feedback signal occurs when the time interval between the coarse feedback and command signalsis less than the time ineterval as dictated by theswitching of the single shot circuit, including the flip flop SS. If the l to 0 signal changes in the coarse feedback and coarse command signals CFB and CC before the single shot circuit, including the flip flop SS, times out, a 0 will be present at the E outputs of the flip flops CC and PB before the signals at the toggles T of the flip flop FWD and REV changes from 1 to 0 in response to the change in the output of the NAND N10, as previously described. The 0 at the E output of the flip flops CC and EB respectively will cause the K inputs of the flip flops REV and FWD respectively to be 0 when the signal input to the respective toggles changes from 1 to 0 so that neither of the flip flops FWD or REV will switch OFF to cause the motor to be energized.

The flip flops FWD and REV, when in the ON state, will permit the ANDS A4 and A6 to be controlled by the signals in the fine comparator circuit. The crossover from the control in response to the coarse feedback signal to the fine feedback signal is made to'occur when the linear axis is approximately 5 inches from the desired position, or where the coarse error is equivalent to 12 coarse counts by the interval provided by the timing circuit including the flip flop SS. During positioning in response to the coarse error signal, the ANDS A3 or A5 will cause the deceleration module 62 to be supplied with a signal that is ON 20 percent of the time and OFF percent of the time, regardless of the magnitude of the position error. When the control is switched to respond to the find feedback signal, the sources FWP and REP will cause the ANDS A4 or A6-to supply the deceleration module 62 with a signal that is on 20 percent of the time and OFF 80 percent of the time.

Thus the energization of the motor will notchange during cross-over from positioning in response to the coarse error signal to positioning in response to the fine error signal. When the fine error signal becomes less than 200 counts,-the deceleration module 62 will cause theenergization of the motor 26 to be progressively decreased in response to a progressively decreasing fine error signal as the machine moves into its preprogrammed position relative to the workpieces 11 and 12.

The reference signal REF appears. as'a 500 nanosecond pulse which is generated by the 500 l-lZ voltage wave as the polarity of the voltage changes from positiveto negative. The signal REF is used to reset the counters 38 and 39. The 500 HZ reference voltage provides the inputs to the resolvers 44 and 45 and the resolvers 44-47 are adjusted to have their outputs in phasewith the coarse and fine command signals when the pin and the machine l'are at the end position 20 and the coarse and fine command counters 39 and 38 provide command signals of 500 HZ. Thus if a position equivalent to a count less than 500 is required, i.e.,

250, the machine will tendto move upstream. However, other switching circuits,not shown, will prevent the machine-l0 from moving upstream beyond the position so the machine 10 will wait at the end 20 until the pin 17 is moved the required 250 units. distance into the work station. If the next required position requires a count of 350, the machine 10 will movedownstream the required distanceto satisfy the 350 count. Finally, if the next requiredposition requires a count of lOO, the machine 10 will move upstream the required distance'to satisfy the 100 count.

HOLD-10o CIRCUIT. Referring to FIGS. 1 and 4, the hold and jog circuit 1 in FIG. 4 provides the functions included inn the holdjog module 34 and the switch module 61 and receives the l MHZ, the 500 KHZ and the 500 HZ reference input signals fromm the timing module 42. The

forward switch JF, the jog reverse switch JR and the fast jog switches FJ are open, so that the NANDS N21, N37, N50, N56 and N43 respectively receive a 0 input and provide a l output. The flip flop SS1 is in an ON state and supplies a l at its E output and a O at its Eoutput. The l at the E output of the flip flop SS1 is supplied to an input of the NAND N22 which also receives a 1 input at its other two inputs in a manner which will be later described, so that the NAND N22 provides a 0 input to the NAND N23 and causes the NAND N23 to have a 1 output. The 1 output of the NAND N23 causes the NAND N24 to supply a 0 to the J input of the flip flop F1 and a 0 to the input of the NAND N25 so that the NAND N25 supplies a l to the K input of the flip flop F1 and the set input Sof the flip flop F2. The flip flop F1 in response to the inputs at its J and K inputs supplies a 0 at its E output and a l at its E output. The 0 at the E output of the flip flop F1 is supplied to the K inputs of the flip flops F3 and F4. The l at the E output of the flip flop F1 is'supplied to the K input of the flip flop F2 andas an inputBC to the coarse and fine comparator circuits shown in FIG. 2. The l to the K input of the flip flop F2 causes the flip flop-F2 to provide a l at its E output which is supplied to the inputs of the NANDS N32 and N33.

During standby conditions, the previously set flip flops CCR and FCR have a l at their respective E outputs which. are respectively supplied through the NANDS N28 and N31 to thecounters 39 and 38. The

flip flops F3 and F4 in response to the 0 at their K inputs have a 0 at their E'outputs. The 0 at the E'output of the flip flop F3 causes the NAND'N26 to supply a 1 input to the NAND N27 so that theNAND N27 supplies a O to the K input of the flip flop CCR. The'O at the E output of the flip flop F4 causes the NAND N29 to supply a 1 input to the NAND N30 so that the NAND N30 supplies a 0 to the K input of the flip flop FCR. The flip flop F3 receives the coarse feedback signal CFB at its toggle input T and the flip flop FCR receives the fine feedback signal FFB at its toggle T input. The 500 HZ signal is connected through the NANDN59 to supply inputs to the toggle inputs T of the flip flops F l and F2. The 500 KHZ source supplies an input through aNAND N58 to the set inputs ofthe flip flops CCR and FCR as well as'an input 1 of the NANDS N26 and N29. The lMHZ source supplies an input through the NAND N57 to the toggle inputs T of the flip flops'CCR and FCR so that the respective flip flops CCR and FCR supply outputs as described.

The hold period is initiated by closing the hold switch H so that a l is supplied to the input of the NAND N21.

timing circuit T, is arranged to act as a single shot multivibrator. The l to 0 change to the input T of the flip flop SS1 switches the flip flop SS1 so that a 0 appears at its E output, which causes the NAND N22 to switch, and provide a 1 output as input to the NAND N23. The l to 0 signal change from the NAND N21 to the input T of the flip flop SS1 also causes the flip flop SS1 to switch and supply a O to 1 signal change at its E output, which change is delayed for 380 milliseconds and supplied by the timing circuit T as a l to 0 change to the set input S of the flip flop SSLThe 0 signal to the input S'of the flip flop SS1 causes the flip flop SS1 to switch and again supply a 1 at its output E and a O at its output E, so that for 380 milliseconds after the hold switch H is closed, a 0 appears at the output E of the flip flop SS1. The 0 output of the NAND N23 is first inverted by the NAND N24 and'supplied as a l to the J input of the flip flop F1 and again inverted by the NAND N25 and supplied as a 0 to the K input of the flip flop F1 and the S input of the flip flop F2. Flip flops F1 and F2 have their toggle inputs T connected through the NAND N59 to receive the 500 HZ signals so that at an appropriate 1 to 0 signal change at their inputs T, the flip flops F1 and F2 switch so that the flip flop F1 supplies a l at its E output and a 0 at its E output. The

l at the E output of the flip flop F1 is supplied to the inputs K of the flip flops F3 and F4 so that the flip flops F3 and F4 are conditioned to be switched upon a l to 0 change at their toggle T inputs. The 0 at the E input of the flip flop F1 is supplied to the K input of the flip flop F2 and as the signal BC to the comparators 59-60.

The signal BC, which is supplied to the set inputs S of the flip flops FWD and REV and the NANDS N15 and N19 in the comparator circuits shown in FIG. 2, prevents the switching of the flip flops FWD, REV, F FWD and FREV to their OFF states and thus prevents the circuits within the comparators 59-60 from switching in response to the command signals and feedback signals. The flip flop F2 in response to the 0 at its S input supplies a 0 at its E output which causes the NANDS N32 and N33 to have a l'output, the NANDS N34 and N35 to have a 0 output and the NAND N36 to'have a 1 output. The output of the .NANDS N35 and N36 are respectively supplied to the reverse and forward inputs R and F of the deceleration module 62 which, in response thereto, interrupts the energization of the motor 26 so that the motor 26 begins to coast to a stop. The motor 26 causes the rotation of the'feed- I back resolvers 44 and 45. The resolvers 46 and 47 have from 1 to 0, the flip flops F3 and F4 switch ON and prc: vide a l at their associated E outputs. The l at the E outputs of the flip'flops. F3 and F4,issupplied as an input to the NANDS N26 and N29 respectively. The

NANDS N26 and N29 also receive an'input through the NAND N58 from the 500 KHZ pulse source so that when the output of the NAND N58 changes from to l, the NANDS N26 and N29 respectively will provide 0 inputs to the NANDS N27 and N30 and cause the NANDS N27 and N30 to switch and provide a 1 to the K inputs of the flip flops CCR and FCR. The 1 output of the NAND N58, which caused the NANDS N27 and N30 to have I outputs is also supplied as an input to the set inputs S of the flip flops CCR and FCR so that the flip flops CCR and FCR are conditioned to switch and supply a 0 at their associated E outputs upon a suitable l to 0 change from the lMHZ source through the NAND N57 at their associated inputs T which occurs 500 nanoseconds after the signal change at their set in- P t .4

The 0 at the E outputsof the flip flops CCR and FCR, which are respectively supplied to the set inputs S of the flip flops F3 and F4, causes the flip flops F3 and F4 to switch and again supply a 0 at their associated E outputs. The 0 at the E outputs of the flip flops F3 and F4 is respectively supplied to the K inputs of the flip flops CCR and FCR through the associated NANDS fact that the flip flops F3 and F4 are receiving a 1 to 0 N26-N30. Thus 500 nanoseconds after the flip flops CCR and FCR are switched to supply a O at their associated E. outputs, a signal change of Ho 0 at the S input of the flip flops CCR and FCR from the 500 KHZ source through the NAND N58 causes the flip flops CCR and FCR to switch and again supply a l at the associated E outputs. Thus as the motor M coasts to stop, the counters 38 and 39 will be reset with a 0 pulse that has a 500 nanosecond duration each time the coarse and the fine feedback signals CFB and FFB respectively change from 1 to O, which occurs at a rate of 500 cycles per second or approximately 190 times during the 380 millisecond interval as determined by the switching of the flip flop SS1.

As previously described, the single shot flip flop SS1 switches to provide a l at its E output 380 milliseconds after the switch H is closed. The l at the E output of the flip flop SS1 switches the NANDS N22-N25 so that the NAND N24 supplies a O to the J input ofv the flip flop F1 and the NAND N25 supplies a l to the input signal change at their toggle inputs T from the feedback signals CFB and FFB. The 0 to 1 change at the E output of the flip flop Fl, which is supplied to the input K of the flip flop F2, causes the flip flop F2 to switch to its standby state when the signal at tis toggle input T from the NAND N59 changes from 1 to 0. The l atthe E output of the flip flop F2 removes the blocking signal BC to the comparators 59-60 so that the operation of the circuitry within the comparators 59-60 is restored. The 1 signal at the E output of thee flip flop F2, when the flip flop F2 is reset, permits the NANDS N32 and N33 to have a 0 output, the NANDS N34 and N35 to have a l outputand theNAND N36 to have a O'output so that the outputs of the NANDS N35 and- N36 are in their standby condition.

The motor M may be caused to operate in a jogging mode either in the forward direction when the jog forward switch JF is closed, or in the reverse direction when the jog reverse switch JR is closed. During standby conditions, that is, when both the switches JF and JR are open, the forward and reverse jog circuits will be conditioned as follows. The NAND N37 will have a 0 input and supply a 1 output to the NAND N38 and the NAND N40. The NAND N38 is connected to the NAND N39 so that the NANDS N38 and N39 act as a NAND memory. The NAND N will have a 0 input and therefore supply a 1 input to the NANDS N51 and N40. The NAND N51 is connected to the NAND N52 so that the NANDS N51 and N52 actas a NAND memory. The NAND N40, during standby,

has a l on all of its outputs and supplies a 0 to a circuit that the NANDS N38 and N51 have a 0 output and the NANDS N39 and N52 have a 1' output. The 1 output of the NANDS N39 and N52 are respectively supplied to a pair of inputs of the NAND N22 in the hold circuit which permits the NAND N22 to be switched in response to the l to 0 signal change from the E output of the flip flop SS1 when the switch H is closed, as previously described. The 0 outputs of the NANDS N38 S of the flip flop F2 and a l to the input K of the flip flop F 1 so that the flip flops F1 and F2 are conditioned to switch to their standby states upon the receipt of the suitable l to 0 at their inputs T from the 500 HZ source through the NAND N59. When the flip flops F l and F2 are in their standby states, the E output of the flip flop F1 is 0 and the E outputs of the flip flops F l and F2 are l. The 0 at the E output of the flip flop Fl, which is supplied to the K inputs of the flip flops F3 and F4, causes the flip flops F3 and F4 to remain in their OFF states so that their E outputs are a continuous 0 in spite of the and N51, which are respectively supplied as inputs to the NANDS N47 and N53, cause the NANDS N47 and N53 to have a 1 output. The output of the NAND N47 is supplied to an input of the NAND N48 which also receives a 1 input from the NAND N52 so that the NAND N48 supplies a 0 output which is inverted by the NAND N49 and supplied as a 1 input to the NAND N34. The 0 output of the NAND N51 causes the NAND N53 to have a 1 output which is supplied as an inputto the NAND N54. The NAND N54 also receives a l at its other input from the NAND N39 so that the NAND N54 supplies a 0 input to the NAND N55 andbe pulsed to and cause the NAND N32 to provide a ,1 output pulse; Similarly, when the motor 26 is to be rotated in a reverse directiom-the signal at the R output of the comparators 59-60 will be pulsed to 0 and cause the NAND N33 to provide a 1 output pulse. When the NAND N32 has a 0. output,.the output of the NAND N34 will be 1. and the output of the NAND N36 0,

which is supplied to the F input of a deceleration module 62. When the NAND N33 has a 0, output, the

.NAND N35 will have a '1 output, which is supplied to the R input of the deceleration module 62. A switch in the output of the NAND N32 from the 0 to '1 will cause the output of the NAND N36 to switch from 0 to l and the deceleration module 62 to provide an output which will cause the motor 26 to operate in the forward direction. Similarly, a change in the outputof the NAND N33 from 0 to '1 will cause the output of the NAND .N35 to switch from 1 to O and the deceleration module tions. The outputs of the NANDS N42 and N43 are respectively connected to the toggle inputs'T of the flip flops SS2 and SS3. The flip flops S82 and SS3 have their E outputs connected to supply al input to the NAND N46. The flip flop SS2 has its E output connected through a time delay circuit consisting of an adjustable resistor R and a capacitor C to an input of the NAND N44 which in turn has its output connected to the set input S of the flip flop SS2. The flip flop SS3 has its E output connected through 'a time delay circuit consisting of an adjustable resistor R and capacitor C to an input of the NAND N45 which has its output connected to the set input S of the flip flop SS3..When the flip flops SS2 and SS3 are s et, they respectively supply a l at their E outputs and a 0 at their E outputs. The NAND N46 in response to the l at the E outputs of the flip flops SS2 and SS3 provides a 0 input to the NANDS N47 and N53 which prevents the NANDS N47 and N53 from being switched when the outputs of the NANDS N38 and N51 become 1 as will be later described. I

be switched when the output signal pulses through the- Schmitt trigger ST2 change to 1. The 0 input to the NAND N43 prevents the NAND N43 from switching when the output pulses of the Schmitt trigger ST2 switches from 0 to l. v I Y The motor 26 will be'caused to operate in the jogging mode in the forward direction .by closing switch J F so that the input to the NAND N37 changesfrom 0 to l and the NAND N37 providesa 0 output which causes the outputs of the NANDS N38 and N40 to become 1. The change in the output ofthe NAND N38 for a short time period afterr the switch JF is closed, i.e., 50 milliseconds, does not cause any change in the remaining portions of the circuit as the NAND N39 continues to receive a0 input from the NAND N41 so its output remains l and the NAND N47 continues to receive a 0 input from the NAND N46 so its output remains l;

The circuitry within the jog speed module 68 is arranged so that approximately 50 milliseconds after the output of the NAND N40 changes from 0 to l, the output of the Schmitttriggers STl and ST2 will respectively change so that the Schmitt trigger STl provides a continuous 0 output and the Schmitt trigger ST2 provides a pulsing 1 output. The 0 signal output of the Schmitt trigger ST] is inverted by the NAND N41 and supplied. as a 1 input to the NAND N39. As all of the inputs of the NAND N39 are now 1, the NAND N39 output switches to 0 which is supplied as an input to the NANDS N22 and N54. The 0 input to the NAND N22 causes the NAND N22 to switch and provide a 1 output and the NAND N23 to have a 0 output. The 0 output of the NAND N23 is first inverted by'the- NAND N24 and supplied asa l to the J input of the flip flop F1 and is again inverted by the NAND N25 and supplied as a 0 to the K input of the flip flop F1 and to theset input S of the flip flop F2. The flipflops F 1 and F2 have their toggle inputs T connected through the NAND N59 to receive signal pulses from the 500 HZ source so that upon the receipt of an appropriate 1 to 0 signal change at their toggle inputs T, the flip flops F1 and F2 switch so that the'flip flop Fl supplies a 1 at its E output and a O at its E output. The 0 at the E output of the flip flop F l is supplied to the K input of the flip flop F2 and as asignal BC tothe comparators 59 -60. The signal BC causes. the operation of the circuitry within the compar ators 59-60 to be blocked so that the signals at the R and F outputs of the comparators 59-60 are a continuousl. The flip flop F2, in response to the O at its S input, supplies a 0 at its E output which causes the NANDS N32 and N33 to each have a 1 output so that the switching of the NANDS N34 and N35 is controlled by the output signals from the NANDS N49 and N55. When the motor 26 is energized to operate in a jogging mode, in a manner which will be later described, the feedback resolvers 46 and 47 will provide coarse and fine feedback signals CFB and FFB as inputs to the input toggles T of the flip flops CCR and FCR respectively. The 1 to 0- change in the signals CCR and FCR to the toggles T of the flip flops CCR and FCR causes the flip flops CCR and FCR to switch and provide a l at their associated E outputs which is respectively supplied as inputs to the NANDS N26 and N29. The NANDS N26 and N29 also receive input pulses through the NAND N58 from the 500 KHZ source so that when the output of the NAND N58 changes from 0 to l, the NANDS N26 and N29 will provide 0 inputs to the respective NANDS N27 and N30. The NANDS N27 and N30 in response to the 0 inputs respectively provide a l to the K inputs of the flip flops CCR and FCR. The 1 output of the NAND N58 which caused the NANDS N27 and N30 to have 1 outputs is also supplied as an input to the inputs S of the flip flops CCR and FCR so that the flip flops CCR and FCR are condi tionedto be switched and supply a 0 at their associated E outputs upon the receipt of a suitable l to 0 change from the NAND N57 at their toggle inputs T which occurs 500 nanoseconds after the 0 to 1 signal. change at their associated set inputs S. The 0 at the E outputs of 

1. A circuit for controlling the energization of an electric motor comprising: a first capacitor, means for increasing the level of a charge across the first capacitor at a first predetermined rate to a predetermined level when the circuit is initially actuated, means for decreasing the level of the charge across the first capacitor from the predetermined level at a second predetermined rate after the circuit is deactuated, a second capacitor, means including a first transistor having a conductive level controlled by the level of the charge on the first capacitor and having electrodes connected in a charging circuit for the second capacitor for causing the rate at which the second capacitor is charged to be controlled by the level of the charge across the first capacitor, means for producing pulses at a frequency controlled by the level of the charge on the first capacitor, said pulse producing means including a programmable unijunction transistor having electrodeS connected so the unijunction transistor is switched to a conductive state by the charge on the second capacitor when the level of the charge across the second capacitor reaches a predetermined value and provides an output pulse and causes the second capacitor to be discharged when the unijunction transistor is switched to its conductive state as the second capacitor is alternately charged by current flow through the first transistor and discharged through the conducting unijunction transistor, means including a second transistor having electrodes connected so the conductive level of the second transistor is controlled by the conductive level of the first transistor for providing an output signal change when the conductive level of the first transistor causes the charge on the second capacitor to equal the predetermined value, and timing means having an input receiving the output pulses of the pulse producing means and providing constant width output pulses at the same frequency as the output pulses of the pulse producing means.
 2. The circuit as recited in claim 1 wherein the timing means includes a pair of flip flops which respectively provide output pulses of different widths in response to the input pulses from the pulse producing means.
 3. The circuit as recited in claim 1 wherein the means for increasing and decreasing the level of the charge across the first capacitor includes a third transistor that is switched to a nonconductive state when the circuit is actuated and to a conductive state when the circuit is deactuated. 